1. Field of the Invention
The present invention relates to a thin film transistor substrate and a method for manufacturing the same.
2. Description of Related Art
In a display device using liquid crystal or organic EL, a large number of pixels are arranged in matrix. A Thin Film Transistor (hereinafter referred to as TFT) is used as a switching device for each of the pixels. The TFT is connected with a pixel electrode, a scan signal line and an image signal line for driving the liquid crystal.
A conventional TFT has mainly been using amorphous silicon (hereinafter referred to as a-Si) film as a material for semiconductor layer. However in recent years, TFTs using poly crystalline silicon (hereinafter referred to as p-Si) film as a material for semiconductor layer are planed to be in practice. This is because that the TFT using p-Si as semiconductor layer has high mobility and favorable semiconductor characteristic. Accordingly not only for a switching device, but such TFT can be used as a drive circuit device for driving the switching device. By forming a drive circuit over an array substrate, there are favorable advantages such that an IC (Integrated Circuit) for driving is not required to be installed. Thus it is expected to reduce the cost, improve functionalities and achieve advanced integration.
For a liquid crystal display, an array substrate 110 is formed by forming TFTs, signal lines and pixel electrodes in a desired position and configuration over an insulating substrate as shown in FIG. 9.
A display region 111 and a frame region 112 surrounding the display region 111 are provided on the array substrate 110. In the display region 111, a plurality of gate lines (scanning signal lines) 113 and a plurality of source lines (display signal lines) 114 are formed. The plurality of gate lines 113 are provided in parallel. Likewise, the plurality of source lines 114 are provided in parallel. The gate lines 113 and the source lines 114 are formed to cross each other. The gate lines 113 and the source lines 114 are orthogonal to each other. Further, a region surrounded by adjacent gate lines 113 and the source lines 114 is a pixel 117. Accordingly the pixels 117 are arranged in matrix in the array substrate 110.
Further, in the frame region 112 of the array substrate 110, a scanning signal drive circuit 115 and a display signal drive circuit 116 are formed. The gate lines 113 extend from the display region 111 to the frame region 112. Further, the gate lines 113 are connected with the scanning signal drive circuit 115 at the edge of the array substrate 110. Likewise, the source lines 114 extend from the display region 111 to the frame region 112. Further, the source lines 114 are connected with the display signal drive circuit 116 at the edge of the array substrate 110. An external line 118 is connected near the scanning signal drive circuit 115 via the terminal connecting portion. Further, an external line 119 is connected near the display signal drive circuit 116 via the terminal portion. The external lines 118 and 119 constitute wiring board such as FPC (Flexible Printed Circuit).
Various signals are externally supplied through the external lines 118 and 119 to the scanning signal drive circuit 115 and the display signal drive circuit 116, respectively. In accordance with an external control signal, the scanning signal drive circuit 115 supplies a gate signal (scanning signal) to the gate line 113. In response to the gate signal, the gate lines 113 are selected one by one. The display signal drive circuit 116 supplies a display signal (an applied voltage) to the source line 114 based on an external control signal and display data. Thus, an applied voltage corresponding to the display data can be supplied to each pixel 117.
At least one TFT 120 is formed in the pixel 117. The TFT 120 is placed near the crossing point of the source line 114 and gate line 113. The TFT 120 provides an applied voltage to a pixel electrode, for example. Specifically, in response to the gate signal from the gate line 113, the TFT 120, a switching device, is turned on. Thus, the applied voltage is supplied to the pixel electrode connected to a drain electrode of the TFT 120 from the source line 114. Further, an electric field depending on the applied voltage is generated between the pixel and opposing electrodes. Incidentally, an alignment layer (not shown) is formed over the surface of the array substrate 110.
Further, an opposing substrate is placed opposed to the array substrate 110. The opposing substrate may be a color filter substrate, which is placed on the viewing side. A color filter, a black matrix (BM), an opposing electrode, an alignment layer and so on are formed over the opposing substrate. For IPS (In-Plane Switching) or the like, the opposing electrode may be placed on the array substrate 110 side. Furthermore, a liquid crystal layer is held between the array substrate 110 and the opposing substrate. Specifically, liquid crystal is filled between the array substrate 110 and the opposing substrate. Moreover, a polarizing plate and a retardation film or the like are provided to the outside surface of the array substrate 110 and the opposing substrate. Further a backlight unit or the like is provided to a non-visible side of the liquid crystal display panel.
Liquid crystal is driven by the electric field between the pixel and opposing electrodes. Specifically, an alignment direction of the liquid crystal between the substrates varies. That is, the light passed through the polarization plate to become a linear polarization changes its polarization state by the liquid crystal layer. To be more specific, in the transparent region, the light from the backlight becomes a linear polarization by the polarization plate provided to the TFT array substrate side. Then the polarization state of the linearly polarized light changes by passing through the liquid crystal layer.
The amount of light passing through the polarizing plate on the opposing substrate varies according to the polarization state. Specifically, among the transmitted light transmitting the liquid crystal display panel from the backlight unit, the amount of light passing through the polarizing plate on the visible side changes. The alignment direction of the liquid crystal varies according to the applied voltage. Accordingly by controlling the applied voltage, the amount of light passing through the polarizing plate on the visible side can be changed. That is, by varying the applied voltage for each pixel, a desired image can be displayed.
FIGS. 10A and 10B are a plane view and a cross-sectional view showing the configuration of a general top gate type p-Si TFT, respectively. FIG. 10B is a cross-sectional view taken along the line A-B of FIG. 10A. Note that the cross-sectional view of the line C-D of FIG. 10A is same as FIG. 1C.
A TFT 121 is comprised of a semiconductor layer 13 formed on an insulating protective layer 12, over an insulating substrate 11, a gate insulating film 15 formed over the semiconductor layer 13, and a gate electrode 16 formed over the gate insulating film 15. For a bottom-gate a-Si TFT, the positions of the gate electrode 16 and the semiconductor layer 13 are interchanged each other.
In FIG. 10B, the cross-section surface of the semiconductor layer 13 is in trapezoid shape in which the width gets narrowed from the bottom to the top, with its side being tapered shape (a tapered portion 14). The reason for this is described hereinafter. As shown in FIG. 10B, the gate insulating film 15 is formed to cover the semiconductor layer 13. If the cross-sectional shape of the semiconductor layer 13 is rectangle, the gate insulating film 15 has a bad coverage at the side of the semiconductor layer 13, overhanging to form a shade. After that, to dry etch the gate electrode layer to form the gate electrode 16, the gate electrode material deposited under the shade remains as an etching residue. The etching residue causes a problem of shorting-out with adjacent line. Further, if the gate electrode layer is wet etched, there is a problem in that the gate electrode material covering the shade is also etched and the gate electrode 16 is disconnected. To solve such problem, the side of the semiconductor layer 13 is formed in tapered shape.
By forming the side of the semiconductor layer 13 in tapered shape, problems relating to the etching residue and disconnection of the gate electrode 16 can be resolved. However there is another problem generated. That is, by a thin portion (the tapered portion 14) in the film thickness of the semiconductor layer 13, the TFT 121 is turned on at a lower gate voltage than the channel region 132, the main portion of the semiconductor layer 13. Therefore in subthreshold characteristic (Id-Vg characteristic) shown in FIG. 11, there is a problem that a hump is likely to be generated. This makes it difficult to control a threshold voltage (Vth), thereby causing to destabilize the device characteristic of the TFT 121.
To solve such problems, techniques are disclosed in Japanese Unexamined Patent Application Publication No. 2000-77665, Japanese Unexamined Patent Application Publication No. 2003-258262, Japanese Unexamined Patent Application Publication No. 2000-332254 and Japanese Unexamined Patent Application Publication No. 7-326763. In Japanese Unexamined Patent Application Publication No. 2000-77665, Japanese Unexamined Patent Application Publication No. 2003-258262, and Japanese Unexamined Patent Application Publication No. 2000-332254, impurity such as Ar is doped in the tapered portion 14 or the tapered portion 14 is oxidized in order to improve the electric characteristic of the TFT 121. By substantially increasing the electric resistance of the tapered portion 14, the TFT is prevented from turning on in a comparatively low gate voltage. In the technique disclosed in Japanese Unexamined Patent Application Publication No. 7-326763, openings are created in a part of the gate electrode 16 over the tapered portion 14 of the semiconductor layer 13, and an impurity is prevented from introducing in the tapered portion 14. That is, the gate electrode 16 does not exist above the tapered portion 14 and no impurity exist in the tapered region 14. Consequently the tapered portion 14 is unlikely to be influenced by the potential of the gate electrode 16.
However the inventors have found that there is a following problem in the conventional techniques. In the techniques disclosed in Japanese Unexamined Patent Application Publication No. 2000-77665, Japanese Unexamined Patent Application Publication No. 2003-258262 and Japanese Unexamined Patent Application Publication No. 2000-332254, to introduce an impurity in the tapered portion 14 or to oxidize, a new process must be added. Further in the technique disclosed in Japanese Unexamined Patent Application Publication No. 7-326763, if a fixed potential exists in the insulating film or the interface of the insulating film near the tapered portion 14, an inversion layer is likely to be formed due to the fixed potential. Specifically, the technique has improvement effects however there still is a possibility of a problem for generating the hump in the subthreshold characteristic shown in FIG. 11.